1. Field of the Invention
The present invention generally relates to an apparatus for testing IC devices and more particularly to a circuit for inverting the latter half of an expected pattern signal output of a device which is tested by using an IC (integrated circuit) tester.
Among the devices tested by using IC testers, there exist those which output respective expected pattern signals which are inverted in the polarity or waveform for a duration corresponding to the latter half of the pattern. For making decision as to whether or not such type of device under test operates satisfactorily (i.e. whether the device passes the test or fails), it is indispensably required to invert the latter half portion of the expected output pattern of the device under test. The present invention is concerned with a circuit for inverting the latter half of the expected pattern output from the device of the type mentioned above.
2. Description of the Related Art
For having better understanding of the present invention, description will be made in some detail of a decision circuit known heretofore by reference to FIG. 3 of the accompanying drawings.
In FIG. 3, a reference numeral 5 denotes an exclusive-OR circuit (also referred to simply as EXOR), and 6 denotes a flip-flop circuit (also referred to simply as FF). A pattern signal 14 representing a pattern expected to be outputted from a device under test is applied to one input terminal of the EXOR 5 together with an actual output pattern of the device and applied to the other input of the EXOR 5, the output of which is then applied to a terminal D of the flip-flop circuit 6.
The flip-flop circuit 6 samples the output of the EXOR 5 with a decision strobe signal 16 applied to a terminal C, to thereby output a pass/fail signal indicating whether the actual output pattern coincides with the expected pattern, i.e. whether or not the device under test operates successfully or not. More specifically, the pass signal which may be of logic "0" is outputted from the flip-flop or FF 6 when coincidence is found between the expected pattern signal 11 and the actual output pattern signal. On the other hand, when discrepancy is detected between the expected pattern 11 and the output pattern 15, the flip-flop circuit 6 produces as the output the fail signal of logic "1".
Next, operation or function of the decision circuit shown in FIG. 3 will be elucidated by reference to a timing chart shown in FIG. 4 of the accompanying drawings. Referring to FIG. 4, there are shown a waveform of a reference clock signal 12 and that of the expected pattern signal 11 at (a) and (b), respectively. The reference clock signal 12 serves for determining the period of the expected pattern signal 11. Further, the output pattern signal 15 of the device under test may have such a waveform as shown at (c) in FIG. 4 with the strobe signal 16 having a waveform shown at (d) in the figure.
The expected pattern signal 11 and the actual output pattern signal 15 are applied to the inputs of the EXOR 5, as mentioned above, the output of which is latched by the flip-flop 6 with the strobe signal 16, whereby the pass/fail decision signal having such a waveform as shown at (e) in FIG. 4 is outputted from the flip-flop circuit 6. In the case of the illustrated example, the output signal of the flip-flop circuit 6 is shown to be of logic "0" at (f) in FIG. 4, indicating that the output pattern 15 coincides with the expected pattern 11. The period of the decision (i.e. periodical interval at which the decision is made as to whether the device under test passes or fails the test) is determined by the period T.sub.o of the reference clock signal. In other words, the decision-making is done every period or cycle of the reference clock signal. This is a limitation imposed because of the expected pattern 11 being latched and transmitted under the timing of the reference clock 12.
In conjunction with the strobe signal, there is known a double-strobe mode test in which the strobe signal 16 is generated twice at two descrete time points within one period T.sub.o of the reference clock signal 13, as can be seen from FIG. 4 at (g).
Now, let's assume that such a device is to be tested which produces an output signal inverted during the latter half of the expected pattern and which has a higher operation cycle than that of the tester. In that case, the tester will be set to the double strobe mode mentioned above, and it is expected that the result of "pass " is obtained, as shown in FIG. 4 at (e). However, since the expected pattern changes only on the one cycle basis, the result will be an alternate sequence in which "pass" and "fail" alternate with each other, as illustrated at (h) in FIG. 4. For this reason, it is impossible to test a device operating at a high frequency by the IC tester whose maximum operation frequency is lower than that of the device to be tested, to a great disadvantage.